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Category B.6 LOGIC DESIGN

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Current category: Top  ::  ITHEA Classification Structure  ::  B. Hardware  ::  B.6 LOGIC DESIGN
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B.6.1 Design Styles Article ESTIMATION OF PEAK SUSTAINABLE POWER CONSUMPTION FOR SEQUENTIAL CMOS CIRCUITS Abstract: The reliability and the cost of electronic circuits are closely connected to the maximum power dissipated by them. Tools for evaluating the worst case power consumption of sequential circu 
B.6 LOGIC DESIGN Article IMPLEMENTATION OF A HEURISTIC METHOD OF DECOMPOSITION ... Abstract: An original heuristic algorithm of sequential two-block decomposition of partial Boolean functions is researched. The key combinatorial task is considered: finding of suitable partition on  
B.6 LOGIC DESIGN Article LARGE VLSI ARRAYS – POWER AND ARCHITECTURAL PERSPECTIVES Abstract: A novel approach to power reduction in VLSI arrays is proposed. This approach includes recognition of the similarities in architectures and power profiles of different types of arrays, adap 
B.6.3 Design Aids Article MULTIPLE FOLDING OF VLSI REGULAR STRUCTURE VIA BOOLEAN SATISFIABILITY Abstract: The problem under consideration is to reduce the area of the layout of regular VLSI structures by means of their folding. A novel reformulation of the folding problem as the Boolean satisfi 
B.6.3 Design Aids Article OPTIMIZING PROGRAMMABLE LOGIC ARRAYS USING THE SIMULATED ANNEALING ALGORITHM Abstract: In the paper the programmable logic array (PLA) topological optimization problem is dealt with using folding techniques. A PLA folding algorithm based on the method of simulated annealing is 
B.6.3 Design Aids Article Program Invariants Generation over Polynomial Ring using Iterative Methods. Abstract: A solution for program polynomial invariant generation problem is presented. An iteration upper approximation method that was successfully applied on free algebras in this paper was adopted  
B.6.2 Reliability and Testing Article SAT-BASED METHOD OF VERIFICATION USING LOGARITHMIC ENCODING Abstract: The problem under discussion is to check whether a given combinational network realizes a system of incompletely specified Boolean functions. SAT-based procedure is discussed that formulate 
B.6.2 Reliability and Testing Article SAT-BASED METHOD OF VERIFICATION USING LOGARITHMIC ENCODING Abstract: The problem under discussion is to check whether a given combinational network realizes a system of incompletely specified Boolean functions. SAT-based procedure is discussed that formulate 
B.6.3 Design Aids Article SCALAR CHOICE CRITERIA'S USAGE FOR DETERMINATION OF THE OPTIMUM SWITCHING ... Abstract: An approach to the optimum switching scheme’s choice is proposed. It is based on the scalar choice criteria. Problem of the multistage switching system's structure's determination is solv 
B.6.2 Reliability and Testing Article SEARCH ALGORITHM FOR SHORTEST SYNCHRONIZING SEQUENCES USING BOOLEAN SATISFIABILI Abstract: The problem under consideration is to find a synchronizing sequence for a logic network with memory. A novel method is proposed that is based on formulation of the task as the Boolean satisf 
B.6.3 Design Aids Article SIMPLE CONSTRAINED FOLDING OF PROGRAMMABLE LOGIC ARRAYS OF SPECIAL TYPE Abstract: In the paper the constrained folding problem is investigated for programmable logic array (PLA) of special architecture type. Constraints applied to folding are given which are imposed by t 
B.6.2 Reliability and Testing Article SIMULATION-BASED APPROACH TO VERIFICATION OF ... Abstract: A verification task of proving the equivalence of two descriptions of the same device is examined for the case, when one of the descriptions is partially defined. In this case, the verifica 
B.6.3 Design Aids Article SOME ASPECTS OF CHOICE OF SWITCHING SCHEME FOR CONSTRUCTION OF OPTICAL ... Abstract: Some aspects of choice of switching scheme for optical signals' square switching system's construction of big capacity are considered in the work. Variant based on scalar criteria of choic 
B.6.2 Reliability and Testing Article USING SAT FOR COMBINATIONAL IMPLEMENTATION CHECKING Abstract. The problem of checking whether a system of incompletely specified Boolean functions is implemented by the given combinational circuit is considered. The task is reduced to testing out if t 

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