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Category B.7 INTEGRATED CIRCUITS

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Current category: Top  ::  ITHEA Classification Structure  ::  B. Hardware  ::  B.7 INTEGRATED CIRCUITS
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B.7.0 General Article BOTTLENECK PROBLEM SOLUTION USING BIOLOGICAL ... Abstract: Every high resolution imaging system suffers from the bottleneck problem. This problem relates to the huge amount of data transmission from the sensor array to a digital signal processing ( 
B.7.1 Types and Design Styles Article DESIGN, IMPLEMENTATION, AND TESTING OF A MINIATURE SELF-STABILIZING CAPSULE ... Abstract: Video capsule endoscopy (VCE) enables examination of the small intestine. In large-lumen organs of the gastrointestinal (GI) tract (e.g. the stomach and the colon), the capsule tumbles aroun 
B.7.3 Reliability and Testing Article ESTIMATION OF PEAK SUSTAINABLE POWER CONSUMPTION FOR SEQUENTIAL CMOS CIRCUITS Abstract: The reliability and the cost of electronic circuits are closely connected to the maximum power dissipated by them. Tools for evaluating the worst case power consumption of sequential circu 
B.7 INTEGRATED CIRCUITS Article LARGE VLSI ARRAYS – POWER AND ARCHITECTURAL PERSPECTIVES Abstract: A novel approach to power reduction in VLSI arrays is proposed. This approach includes recognition of the similarities in architectures and power profiles of different types of arrays, adap 
B.7.0 General Article LOW-POWER TRACKING IMAGE SENSOR BASED ON BIOLOGICAL ... Abstract: This paper presents implementation of a low-power tracking CMOS image sensor based on biological models of attention. The presented imager allows tracking of up to N salient targets in the  
B.7.2 Design Aids Article MACROMODELING FOR VLSI PHYSICAL DESIGN AUTOMATION PROBLEMS Abstract: The paper summarizes the authors methodology for solving the intractable combinatorial problems in physical design of electronic devices: VLSI, SOC, PCB and other. The Optimal Circuit Reduc 
B.7.2 Design Aids Article OPTIMIZING PROGRAMMABLE LOGIC ARRAYS USING THE SIMULATED ANNEALING ALGORITHM Abstract: In the paper the programmable logic array (PLA) topological optimization problem is dealt with using folding techniques. A PLA folding algorithm based on the method of simulated annealing is 
B.7.1 Types and Design Styles Article SELF-ASSEMBLY PROCESS FOR INTEGRATED CIRCUITS BASED ON CARBON NANOTUBES ... Abstract: New methods are needed to create integrated circuits which are able to overcome the inherent problems in the miniaturization process. These problems are mainly technological and economical; 

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