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Category B.6.2 Reliability and Testing

Built-in tests Error-checking Redundant design Test generation Testability
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Current category: Top  ::  ITHEA Classification Structure  ::  B. Hardware  ::  B.6 LOGIC DESIGN  ::  B.6.2 Reliability and Testing
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Article SAT-BASED METHOD OF VERIFICATION USING LOGARITHMIC ENCODING Abstract: The problem under discussion is to check whether a given combinational network realizes a system of incompletely specified Boolean functions. SAT-based procedure is discussed that formulate 
Article SAT-BASED METHOD OF VERIFICATION USING LOGARITHMIC ENCODING Abstract: The problem under discussion is to check whether a given combinational network realizes a system of incompletely specified Boolean functions. SAT-based procedure is discussed that formulate 
Article SEARCH ALGORITHM FOR SHORTEST SYNCHRONIZING SEQUENCES USING BOOLEAN SATISFIABILI Abstract: The problem under consideration is to find a synchronizing sequence for a logic network with memory. A novel method is proposed that is based on formulation of the task as the Boolean satisf 
Article SIMULATION-BASED APPROACH TO VERIFICATION OF ... Abstract: A verification task of proving the equivalence of two descriptions of the same device is examined for the case, when one of the descriptions is partially defined. In this case, the verifica 
Article USING SAT FOR COMBINATIONAL IMPLEMENTATION CHECKING Abstract. The problem of checking whether a system of incompletely specified Boolean functions is implemented by the given combinational circuit is considered. The task is reduced to testing out if t 

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